(1) Field of the Invention
The present invention relates to a decoding apparatus which performs decoding of encoded data and an encoding apparatus which performs encoding, in data compression and data expansion of audio and image.
(2) Description of the Related Art
Conventionally, in a decoding apparatus which decodes sound, image and so on, encoded data is outputted to an inverse quantization unit after being decoded in a fixed-length decoding unit and a variable-length decoding unit, as shown in Japanese Laid-Open Patent Application No. 6-69812 (Section 5, FIG. 1), for example. Furthermore, in an encoding apparatus which performs encoding, quantized data is encoded by a fixed-length encoding unit and a variable-length encoding unit, and compressed data is outputted.
Furthermore, in general, a decoding apparatus which performs fixed-length decoding and variable-length decoding is structured in the manner shown in FIG. 1. The decoding apparatus in the diagram includes a processor 900, an input data memory 910, and input data memory I/F 920, a decoding circuit 930, an output data memory 940, and an output data memory I/F 950.
The processor 900 accesses the input data memory 910 in order to perform the processing of encoded data stored in the input data memory 910. The processing of data described here includes the deletion of a marker. In the case of JPEG, various markers are defined, as markers indicate the existence of a header or a table. A marker is a specific bit sequence such as “FF”, and indicates that the 1-byte data following it is not data, but a control code. In the decoding of encoded data, when a specific bit sequence identical to the marker exists within the encoded data, distinguishing data (for example, “00”) indicating that such specific bit sequence is not a marker is added. For example, although the “FF” in “FF01” within the encoded data is a marker, “FF” in “FF00” is not a marker, but data. The processor 900 deletes such distinguishing data as “00”.
The decoding circuit 930 outputs a data request signal to the input data memory I/F 920 in order to read the data to be decoded, from the input data memory 910.
In the case where accessing by the processor 900 and the decoding circuit 930 conflict, the input data memory I/F 920 permits the accessing by one side, and places the accessing of the other on stand-by.
Upon reading the data to be decoded from the input data memory 910, the decoding circuit 930 carries out the decoding, outputs the result to the output data memory 940, and outputs, to the output data memory I/F 950, a data output signal indicating that the output data is valid.
The output data memory I/F 950 outputs the write address to the output data memory 940.
Thus the decoding apparatus which decodes the data in the input data memory 910 and stores the result in the output data memory 940 operates in such manner.
In the conventional decoding apparatus, the processor deletes the distinguishing data indicating a non-marker, and writes the result in the input data memory, after which the decoding circuit performs decoding and the decoded result is outputted to the output data memory. Because the deletion of the distinguishing data indicating a non-marker is performed using the processor, input and output between the memory and the processor, as well as the deletion performed by the processor become a necessity, so there exists the problem of deterioration of decoding performance.